1. Field of the Invention
This invention relates generally to an encoder and a decoder for transferring data between superconducting circuits and, more particularly, to a superconducting encoder that interleaves clock and data signals onto a common line and a superconducting decoder that decodes the clock and data signals interleaved on the common line to extract the data.
2. Discussion of the Related Art
High-speed fiber-optic data transmission systems are known in the art that have data transmission speeds in the 50-200 Gb/s range. Electrical superconducting logic circuits could be employed in these systems to provide supporting circuits that have the performance necessary at these high speeds. Superconducting circuits use single flux quantum (SFQ) voltage pulses to transmit data at low power, low signal loss and high speed.
Superconducting logic circuits employ Josephson junctions instead of transistors as used in semiconductor-based circuits. A Josephson junction is a weak link between two superconducting materials where electrons tunnel across the junction. As long as the current through the junction is less than a junction critical current, the junction will be superconducting. A bias current is applied to the junction that is below the critical current. When additional current from a signal, is applied to the junction so that the current propagating therethrough exceeds the critical current, the junction will switch to a voltage state. The voltage state will induce a quantum leap in the magnetic phase of the junction, which will create an SFQ voltage pulse across the junction. The duration of the SFQ pulse generated at the junction is determined by fundamental physical constants and is h/2e, where h is Planks constant (6.6262xc3x9710xe2x88x9234 Joule seconds), and e is the fundamental electrical charge (1.602xc3x9710xe2x88x9219 Coulombs). A typical SFQ pulse has a magnitude of about 1 millivolt and a duration of about 2 picoseconds.
The SFQ pulses can be used to transmit data at very high frequencies. The SFQ pulses can be transmitted and amplified by coupling a series of Josephson junctions together to provide a Josephson transmission line (JTL). When a particular Josephson junction in a JTL receives an SFQ pulse from a preceding Josephson junction, the pulse causes the junction to switch so that the SFQ pulse is recreated to continue propagating along the JTL. A discussion of a JTL operating in this manner can be found in U.S. Pat. No. 6,507,234, issued Jan. 14, 2003 to Johnson et al., assigned to the Assignee of this application, and herein incorporated by reference.
SFQ data pulses are transmitted between circuits or chips, such as analog-to-digital converters (ADC), digital filters, digital switches, etc., in these data transmission systems. Because the data pulses are transmitted at such high speeds, the clock signal that provides data timing is transmitted with the data. This is necessary because a global clock signal cannot be used in each chip because the speed of the clock signal is greater than the uncertainty of the timing of the data pulses. In other words, timing jitter in the data transmission is larger than the period of the clock signal, which prevents the ability to accurately time the data. Therefore, the data signal is encoded with the clock signal before it is transmitted. To be useful, the data encoding scheme must involve an overhead of only a few digital gates, and must be consistent with the return to zero data representation inherent in the circuits of interest. Clock recovery circuits or decoders are necessary in the receiving chip to accurately extract the clock signal from the encoded signal.
In general, a digital data stream may contain a long string of Os where there are no transitions between the two digital states from which the phase of the data clock can be recovered. If the clock signal is not properly recovered, the data can not be properly retimed, and thus will be interpreted incorrectly at the receiver.
In one known superconducting system, a 60 Gbs data link between superconducting chips uses fixed-width, RZ voltage pulses. This implies that data can be transferred at an on-chip clock rate of up to 30 GHz, even if the clock and data are multiplexed onto the same line. If only data is sent, this system needs to include a clock recovery circuit such as that based on an instantaneous phase reset of a ring oscillator. However, the clock recovery adds significant jitter to the clock, and is only applicable to data with favorable statistics, such as 8 b/10 b encoded data.
In accordance with the teachings of the present invention, an encoder and a decoder for coding and decoding data transmitted between superconducting circuits is disclosed. The encoder interleaves clock and data signals onto the same signal, and the decoder separates the clock and data signals on the interleaved signal. The SFQ pulses in the clock and data signals need to be 180xc2x0 out of phase so that the data pulses fall between the clock pulses. If the pulses are not 180xc2x0 out of phase, a latching circuit can be used to make the pulses in phase and a delay circuit can be used to delay one or the other of the signals by one half of the clock period.
In the decoder, the interleaved data and clock pulses are applied to a clock input of an RS flip-flop circuit and one input of an AND gate. The output of the flip-flop circuit is the extracted clock signal, and is applied to a delay circuit to be put in phase with the data pulses in the interleaved signal. The delayed clock signal is then applied to the other input of the AND gate, so that when a data pulse occurs in the interleaved signal it aligns with a clock pulse and is output from the AND gate. The clock signal from the flip-flop circuit is sent to the input of the flip-flop circuit through a delay circuit that delays the signal more than one half of the clock period, but less than one clock period.
The clock pulses in the interleaved signal put the flip-flop circuit into the xe2x80x9c0xe2x80x9d state as the SFQ clock pulses are being output therefrom so that when a data pulse between the clock pulses in the interleaved signal is applied to the flip-flop circuit, it is not output as a clock pulse. The delayed clock signal returns the flip-flop circuit to the xe2x80x9c1xe2x80x9d state after the data pulse has passed so that the next clock signal is output from the flip-flop circuit. Therefore, the clock pulses are output from the flip-flop circuit and the data pulses are not output from the flip-flop circuit. If a data pulse is the first pulse to be applied to the flip-flop circuit on the interleaved signal, the decoder will synchronize to the clock pulses when no data pulse (0 bit) is received between two clock pulses.
Additional advantages and features of the present invention will become apparent from the following description and appended claims, taken in conjunction with the accompanying drawings.